git.defcon.no Git - avrfbosd/blob - syncgen/main.c

   1 #include <avr/io.h>
   2 #include <avr/interrupt.h>
   3 #include <util/delay.h>
   4 #define ZERO  PORTB=0b000
   5 #define BLACK PORTB=0b001
   6
   7 //       -----..-----   ^
   8 //      |            |  |
   9 //     -| RST    VCC |-`
  10 //      |            |
  11 //   .--| X1     PB2 |-
  12 //  [ ] |            |  470R
  13 //   '--| X2     PB1 |--^v^v-.
  14 //      |            |       |----> VidOut
  15 //   .--| GND    PB0 |--^v^v-'
  16 //   |  |            |  1kR
  17 //-----  ------------
  18 /*
  19 uint8_t testimg_data[] =
  20 {
  21     0b11111100, 0b00000000, 0b00000011, 0b10000000, 0b00000000, 0b00000000,
  22     0b11111100, 0b00000000, 0b00000011, 0b10000000, 0b00000000, 0b00000000,
  23     0b11111100, 0b00000000, 0b00000011, 0b10000000, 0b00000000, 0b00000000,
  24     0b11111100, 0b00000000, 0b00000011, 0b10000000, 0b00000000, 0b00000000,
  25     0b00000000, 0b00000000,
  26     0b11111100, 0b00000000, 0b00000011, 0b11000000, 0b00000000, 0b00000000,
  27     0b11111100, 0b00000000, 0b00000011, 0b11000000, 0b00000000, 0b00000000,
  28     0b11111100, 0b00000000, 0b00000011, 0b11000000, 0b00000000, 0b00000000,
  29     0b11111100, 0b00000000, 0b00000011, 0b11000000, 0b00000000, 0b00000000,
  30     0b00000000, 0b00000000,
  31     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  32     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  33     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  34     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  35     0b00000000, 0b00000000,
  36     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  37     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  38     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  39     0b00110000, 0b00000000, 0b00000011, 0b01100000, 0b00000000, 0b00000000,
  40     0b00000000, 0b00000000,
  41     0b00110010, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  42     0b00110010, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  43     0b00110010, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  44     0b00110010, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  45     0b00000000, 0b00000000,
  46     0b00110100, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  47     0b00110100, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  48     0b00110100, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  49     0b00110100, 0b11001101, 0b10011011, 0b01101111, 0b00110000, 0b00000000,
  50     0b00000000, 0b00000000,
  51     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b01101100,
  52     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b01101100,
  53     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b01101100,
  54     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b01101100,
  55     0b01101100, 0b01101100,
  56     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b10010010,
  57     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b10010010,
  58     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b10010010,
  59     0b00110000, 0b11101100, 0b11110011, 0b11011001, 0b10110000, 0b10010010,
  60     0b10010010, 0b10010010,
  61     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b10000010,
  62     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b10000010,
  63     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b10000010,
  64     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b10000010,
  65     0b10000010, 0b10000010,
  66     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b01000100,
  67     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b01000100,
  68     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b01000100,
  69     0b00110110, 0b11111100, 0b01100011, 0b00011111, 0b10110000, 0b01000100,
  70     0b01000100, 0b01000100,
  71     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00101000,
  72     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00101000,
  73     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00101000,
  74     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00101000,
  75     0b00101000, 0b00101000,
  76     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00010000,
  77     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00010000,
  78     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00010000,
  79     0b00110110, 0b11011100, 0b01100011, 0b00011001, 0b10110000, 0b00010000,
  80     0b00010000, 0b00010000,
  81     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  82     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  83     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  84     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  85     0b00000000, 0b00000000,
  86     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  87     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  88     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  89     0b00110110, 0b11001100, 0b01100011, 0b00011001, 0b10111111, 0b00000000,
  90     0b00000000, 0b00000000,
  91     0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000,
  92     0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000,
  93     0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000,
  94     0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000, 0b00000000,
  95     0b00000000, 0b00000000,
  96 };
  97
  98 #define testimg_height 15
  99 #define testimg_width 208
 100
 101 #define START1  100
 102 #define END1    115
 103 #define START2  412
 104 #define END2    427
 105 */
 106
 107 #include "avrosdlogo.h"
 108 volatile int rasterline;
 109 volatile uint16_t line;
 110
 111 volatile uint8_t hres;
 112 volatile int renderLine;
 113 int stretch;
 114
 115 void asm_render_line( void ) {
 116         __asm__ __volatile__ (
 117         ".macro outbit p"               "\n\t"
 118                 "BST    __tmp_reg__,7"  "\n\t"  // Store bit 7 to T
 119                 "BLD    r16,1"          "\n\t"  // Load bit T into r16 bit number 4
 120                 "OUT    \\p,r16"        "\n\t"  // Send contents of r16 to %[port]
 121                 "NOP"                   "\n\t"
 122         ".endm"                         "\n\t"
 123
 124                 "ADD    r26,r28"        "\n\t"  // Add register Y to register X, low part
 125                 "ADC    r27,r29"        "\n\t"  // Add high Y to X with carry from low part
 126
 127                 "IN     r16,%[port]"    "\n\t"  // Save port content to register 16
 128                 "RJMP   start_line"     "\n\t"
 129
 130         "loop_byte:"                    "\n\t"  // Notice that in the macro we always use bit 7 and left-shift
 131                 "BST    __tmp_reg__,6"  "\n\t"  // Here we use bit 6 without left-shift to output bit 0
 132                 "BLD    r16,1"          "\n\t"  // of each byte (except the last bit on the line)
 133                 "OUT    %[port],r16"    "\n\t"  // We do not have time for a left-shift, teh "extra cycle" was used for "dec-branch"
 134                 "NOP"                   "\n\t"
 135
 136         "start_line:"                   "\n\t"
 137                 "LD     __tmp_reg__,X+" "\n\t"  // Load from address pointed to by X into temporary register, then increment X-pointer
 138
 139                 "outbit %[port]"        "\n\t"  // Output bit 7 using Macro
 140                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
 141                 "outbit %[port]"        "\n\t"  // Output bit 6 using Macro
 142                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
 143                 "outbit %[port]"        "\n\t"  // Output bit 5 using Macro
 144                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
 145                 "outbit %[port]"        "\n\t"  // Output bit 4 using Macro
 146                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
 147                 "outbit %[port]"        "\n\t"  // Output bit 3 using Macro
 148                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
 149                 "outbit %[port]"        "\n\t"  // Output bit 2 using Macro
 150                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
 151                 "outbit %[port]"        "\n\t"  // Output bit 1 using Macro
 152
 153                 "DEC    %[hres]"        "\n\t"  // Decrement num-bytes-remaining-in-resolution
 154                 "BRNE   loop_byte"      "\n\t"  // Branch to loop6 if %[hres] != zero
 155
 156                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for last bit on the line
 157                 "outbit %[port]"        "\n\t"  // Output bit 0 using Macro.
 158
 159                 "CBI    %[port],1"      "\n\t"  // Clear our "display bit" to ensure we end on black
 160
 161                 :
 162                 : [port] "i" (_SFR_IO_ADDR(PORTB)),
 163                 "x" (testimg_data),
 164                 "y" (renderLine),
 165                 [hres] "d" (hres)
 166         );
 167 }
 168
 169 void hsync(void)
 170 {
 171         line++;
 172         ZERO; _delay_us(4); // sync
 173         BLACK; _delay_us(8);  // Back porch
 174 }
 175
 176 void vsync(uint8_t odd_even)
 177 {
 178         uint8_t a,b;
 179         cli();
 180
 181         // Pre-equalization pulses
 182         b = odd_even ? 6 : 5;
 183         for(a=0; a<b ; a++) // 6x short sync
 184         {
 185                 ZERO;
 186                 _delay_us(2);
 187
 188                 BLACK;
 189                 _delay_us(30);
 190
 191         }
 192
 193         // VSYNC
 194         for(a=0; a<5 ; a++) // 5x long sync
 195         {
 196
 197                 ZERO;
 198                 _delay_us(30);
 199
 200                 BLACK;
 201                 _delay_us(2);
 202
 203         }
 204
 205         // Post-equalization pulses
 206         b = odd_even ? 5 : 4;
 207         for(a=0; a<b ; a++) // 5x short sync
 208         {
 209                 ZERO;
 210                 _delay_us(2);
 211
 212                 BLACK;
 213                 _delay_us(30);
 214
 215         }
 216         line = odd_even ? 5 : 317;
 217         renderLine = 0;
 218
 219         sei();
 220 }
 221
 222 ISR (TIMER0_COMPA_vect)
 223 {
 224         if(line == 310) vsync(0);
 225         else if(line == 622) vsync(1);
 226         else
 227         {
 228                 hsync();
 229                 int t_line = line;
 230                 t_line = ( line > 312 ) ? line - 312 : line;
 231
 232                 if ( t_line > 118 && t_line < 118 + (2*testimg_height) )
 233                 {
 234                         _delay_us(12);
 235                         asm_render_line();
 236
 237                         if( !stretch )
 238                         {
 239                                 stretch = 1;
 240                                 renderLine += hres;
 241                                 if ( renderLine > ((testimg_height*hres)-1) ) renderLine = 0;
 242                         } else stretch--;
 243                 }
 244         }
 245         return;
 246 }
 247
 248 int main(void)
 249 {
 250         rasterline = 0;
 251         line = 0;
 252
 253         hres = testimg_width / 8;
 254
 255         DDRB =0b111;
 256
 257         TCCR0A |= (1<<WGM01)|(0<<WGM00);
 258         TCCR0B |= (0<<WGM02)|(0<<CS02)|(1<<CS01)|(0<<CS00);
 259         TIMSK |= (1<<OCIE0A);
 260         OCR0A = 159;
 261
 262         sei();
 263
 264         // Here, we continue to do nothing...
 265         while(1);
 266 }