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git.defcon.no Git - avrfbosd/blob - syncgen/main.c
2 #include <avr/interrupt.h>
3 #include <util/delay.h>
4 #define ZERO PORTB=0b000
5 #define BLACK PORTB=0b001
13 // '--| X2 PB1 |--^v^v-.
15 // .--| GND PB0 |--^v^v-'
19 #include "avrosdlogo.h"
21 volatile int rasterline
;
22 volatile uint16_t line
;
24 volatile uint8_t hres
;
25 volatile int renderLine
;
28 void asm_render_line( void ) {
29 __asm__
__volatile__ (
30 ".macro outbit p" "\n\t"
31 "BST __tmp_reg__,7" "\n\t" // Store bit 7 to T
32 "BLD r16,1" "\n\t" // Load bit T into r16 bit number 4
33 "OUT \\p,r16" "\n\t" // Send contents of r16 to %[port]
37 "ADD r26,r28" "\n\t" // Add register Y to register X, low part
38 "ADC r27,r29" "\n\t" // Add high Y to X with carry from low part
40 "IN r16,%[port]" "\n\t" // Save port content to register 16
41 "RJMP start_line" "\n\t"
43 "loop_byte:" "\n\t" // Notice that in the macro we always use bit 7 and left-shift
44 "BST __tmp_reg__,6" "\n\t" // Here we use bit 6 without left-shift to output bit 0
45 "BLD r16,1" "\n\t" // of each byte (except the last bit on the line)
46 "OUT %[port],r16" "\n\t" // We do not have time for a left-shift, teh "extra cycle" was used for "dec-branch"
50 "LD __tmp_reg__,X+" "\n\t" // Load from address pointed to by X into temporary register, then increment X-pointer
52 "outbit %[port]" "\n\t" // Output bit 7 using Macro
53 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
54 "outbit %[port]" "\n\t" // Output bit 6 using Macro
55 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
56 "outbit %[port]" "\n\t" // Output bit 5 using Macro
57 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
58 "outbit %[port]" "\n\t" // Output bit 4 using Macro
59 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
60 "outbit %[port]" "\n\t" // Output bit 3 using Macro
61 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
62 "outbit %[port]" "\n\t" // Output bit 2 using Macro
63 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
64 "outbit %[port]" "\n\t" // Output bit 1 using Macro
66 "DEC %[hres]" "\n\t" // Decrement num-bytes-remaining-in-resolution
67 "BRNE loop_byte" "\n\t" // Branch to loop6 if %[hres] != zero
69 "LSL __tmp_reg__" "\n\t" // Left-shift for last bit on the line
70 "outbit %[port]" "\n\t" // Output bit 0 using Macro.
72 "CBI %[port],1" "\n\t" // Clear our "display bit" to ensure we end on black
75 : [port
] "i" (_SFR_IO_ADDR(PORTB
)),
85 ZERO
; _delay_us(4); // sync
86 BLACK
; _delay_us(8); // Back porch
89 void vsync(uint8_t odd_even
)
94 // Pre-equalization pulses
96 for(a
=0; a
<b
; a
++) // 6x short sync
107 for(a
=0; a
<5 ; a
++) // 5x long sync
118 // Post-equalization pulses
119 b
= odd_even
? 5 : 4;
120 for(a
=0; a
<b
; a
++) // 5x short sync
129 line
= odd_even
? 5 : 317;
135 ISR (TIMER0_COMPA_vect
)
137 if(line
== 310) vsync(0);
138 else if(line
== 622) vsync(1);
143 t_line
= ( line
> 312 ) ? line
- 312 : line
;
145 if ( t_line
> 118 && t_line
< 118 + (2*testimg_height
) )
154 if ( renderLine
> ((testimg_height
*hres
)-1) ) renderLine
= 0;
166 hres
= testimg_width
/ 8;
170 TCCR0A
|= (1<<WGM01
)|(0<<WGM00
);
171 TCCR0B
|= (0<<WGM02
)|(0<<CS02
)|(1<<CS01
)|(0<<CS00
);
172 TIMSK
|= (1<<OCIE0A
);
177 // Here, we continue to do nothing...