git.defcon.no Git - avrfbosd/blob - syncgen/main.c

   1 #include <avr/io.h>
   2 #include <avr/interrupt.h>
   3 #include <util/delay.h>
   4
   5 #define ZERO  PORTB &= 0xFC
   6 #define BLACK PORTB |= 0x01
   7
   8 //          -----..-----   ^
   9 //          | ___        |  |
  10 // Com RST -| RST    VCC |-`
  11 //          |            |
  12 // MegaClk -| CLKI  ADC1 |---< VidDetect
  13 //          |            |  470R
  14 // VSwithc -| PB4    PB1 |--^v^v-.
  15 //          |            |       |----> VidOut
  16 //       .--| GND    PB0 |--^v^v-'
  17 //       |  |            |  1kR
  18 //      ---  ------------
  19
  20 #include "avrosdlogo.h"
  21
  22 volatile int rasterline;
  23 volatile uint16_t line;
  24
  25 volatile uint8_t hres;
  26 volatile int renderLine;
  27 int stretch;
  28
  29 void asm_render_line( void ) {
  30         __asm__ __volatile__ (
  31         ".macro outbit p"               "\n\t"
  32                 "BST    __tmp_reg__,7"  "\n\t"  // Store bit 7 to T
  33                 "BLD    r16,1"          "\n\t"  // Load bit T into r16 bit number 4
  34                 "OUT    \\p,r16"        "\n\t"  // Send contents of r16 to %[port]
  35                 "NOP"                   "\n\t"
  36         ".endm"                         "\n\t"
  37
  38                 "ADD    r26,r28"        "\n\t"  // Add register Y to register X, low part
  39                 "ADC    r27,r29"        "\n\t"  // Add high Y to X with carry from low part
  40
  41                 "IN     r16,%[port]"    "\n\t"  // Save port content to register 16
  42                 "RJMP   start_line"     "\n\t"
  43
  44         "loop_byte:"                    "\n\t"  // Notice that in the macro we always use bit 7 and left-shift
  45                 "BST    __tmp_reg__,6"  "\n\t"  // Here we use bit 6 without left-shift to output bit 0
  46                 "BLD    r16,1"          "\n\t"  // of each byte (except the last bit on the line)
  47                 "OUT    %[port],r16"    "\n\t"  // We do not have time for a left-shift, teh "extra cycle" was used for "dec-branch"
  48                 "NOP"                   "\n\t"
  49
  50         "start_line:"                   "\n\t"
  51                 "LD     __tmp_reg__,X+" "\n\t"  // Load from address pointed to by X into temporary register, then increment X-pointer
  52
  53                 "outbit %[port]"        "\n\t"  // Output bit 7 using Macro
  54                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
  55                 "outbit %[port]"        "\n\t"  // Output bit 6 using Macro
  56                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
  57                 "outbit %[port]"        "\n\t"  // Output bit 5 using Macro
  58                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
  59                 "outbit %[port]"        "\n\t"  // Output bit 4 using Macro
  60                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
  61                 "outbit %[port]"        "\n\t"  // Output bit 3 using Macro
  62                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
  63                 "outbit %[port]"        "\n\t"  // Output bit 2 using Macro
  64                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for next bit
  65                 "outbit %[port]"        "\n\t"  // Output bit 1 using Macro
  66
  67                 "DEC    %[hres]"        "\n\t"  // Decrement num-bytes-remaining-in-resolution
  68                 "BRNE   loop_byte"      "\n\t"  // Branch to loop6 if %[hres] != zero
  69
  70                 "LSL    __tmp_reg__"    "\n\t"  // Left-shift for last bit on the line
  71                 "outbit %[port]"        "\n\t"  // Output bit 0 using Macro.
  72
  73                 "CBI    %[port],1"      "\n\t"  // Clear our "display bit" to ensure we end on black
  74
  75                 :
  76                 : [port] "i" (_SFR_IO_ADDR(PORTB)),
  77                 "x" (testimg_data),
  78                 "y" (renderLine),
  79                 [hres] "d" (hres)
  80         );
  81 }
  82
  83 void hsync(void)
  84 {
  85         line++; // Bumping the line-counter as part of hsync gives just the right front-porch ;D
  86         ZERO; _delay_us(4); // sync
  87         BLACK; _delay_us(8);  // Back porch
  88 }
  89
  90 void vsync(uint8_t odd_even)
  91 {
  92         uint8_t a,b;
  93         cli();
  94
  95         // Pre-equalization pulses
  96         b = odd_even ? 6 : 5;
  97         for(a=0; a<b ; a++) // short sync
  98         {
  99                 ZERO;
 100                 _delay_us(2);
 101                 BLACK;
 102                 _delay_us(30);
 103         }
 104
 105         // VSYNC
 106         for(a=0; a<5 ; a++) // long sync
 107         {
 108                 ZERO;
 109                 _delay_us(30);
 110                 BLACK;
 111                 _delay_us(2);
 112         }
 113
 114         // Post-equalization pulses
 115         b = odd_even ? 5 : 4;
 116         for(a=0; a<b ; a++) // short sync
 117         {
 118                 ZERO;
 119                 _delay_us(2);
 120                 BLACK;
 121                 _delay_us(30);
 122         }
 123         line = odd_even ? 5 : 317;
 124         renderLine = 0;
 125
 126         sei();
 127 }
 128
 129 ISR (TIMER0_COMPA_vect)
 130 {
 131         if(line == 310) vsync(0); // End of ODD fields, start vsync'ing
 132         else if(line == 622) vsync(1); // End of EVEN, start vsync'ing
 133         else // In frame. Generate a hsync pulse, then do some drawing :)
 134         {
 135                 hsync();
 136
 137                 int t_line = line; // Reducing line-count complexity by half ;)
 138                 t_line = ( line > 312 ) ? line - 312 : line;
 139
 140                 // Draw the logo-image centered vertically
 141                 if ( t_line > 118 && t_line < 118 + (2*testimg_height) )
 142                 {
 143                         _delay_us(12.3);
 144                         asm_render_line();
 145
 146                         // Stretch the image vertically by repeating the same line twice
 147                         if( !stretch )
 148                         {
 149                                 stretch = 1;
 150                                 renderLine += hres;
 151                                 // Make sure we don't draw anything from RAM after the end of the image
 152                                 if ( renderLine > ((testimg_height*hres)-1) ) renderLine = 0;
 153                         } else stretch--;
 154                 }
 155         }
 156         return;
 157 }
 158
 159 ISR (TIMER1_OVF_vect)
 160 {
 161         // If this interrupt-vector is run, Timer1 has overflowed, and that means
 162         // we have not seen any signal of significant level for quite a while.
 163         // This means Sync-generation is needed...
 164
 165         // Make sure sync-gen is running...
 166         TIMSK |= (1<<OCIE0A); // Enable compare-mach-a interrupt for Timer0
 167         // Open up the switch blocking attiny-generated video:
 168         PORTB |= 0x10;
 169 }
 170
 171 int main(void)
 172 {
 173         rasterline = 0;
 174         line = 0;
 175
 176         hres = testimg_width / 8;
 177
 178         DDRB |= (1<<PB0); // Black/zero level pin/resistor
 179         DDRB |= (1<<PB1); // Color-pin, adds to black level ;)
 180         DDRB |= (1<<PB4); // Control of video-switching. Fuse-bits changes this pin from XTAL2 to PB4
 181
 182         // Timer0 is used to generate hsync (and vsync)
 183         TCCR0A |= (1<<WGM01)|(0<<WGM00); // Set Clear on compare match
 184         TCCR0B |= (0<<WGM02);            // using WGM bits ...
 185         TCCR0B |= (0<<CS02)|(1<<CS01)|(0<<CS00); // Set prescaler to CLK/8
 186         TIMSK |= (1<<OCIE0A); // Enable compare-mach-a interrupt
 187         OCR0A = 159; // 160 "ticks" on 20MHz/8 => 64us. Trigger one early..
 188
 189         // Video detection is done using ADC1 on PB2...
 190         ADMUX |= (1<<ADLAR);   // Left-shifted result.
 191         ADMUX |= (1<<MUX0);    // Select ADC for PB2
 192         ADCSRA |= (1 << ADEN); // Enable ADC
 193         ADCSRA |= (1 << ADPS2)|(1 << ADPS1)|(0<<ADPS0); // set prescaler to 64
 194         DIDR0 |= (1<<ADC1D);   // Disable logic input for PB2
 195
 196         TCCR1 |= (1<<CS13)|(0<<CS12)|(0<<CS11)|(1<<CS10); // Prescale Timer1 to CK/256
 197         // CK/32 @ 20MHz gives 0.05us*256*256 = 3276.8us per Overflow, or 51 lines.
 198         TIMSK |= (1<<TOIE1); // Enable Timer Overflow interrupts for Timer1
 199
 200         sei(); // We are ready to fire interrupts.
 201
 202         // Here, we continue to do nothing...
 203         while(1)
 204         {
 205                 ADCSRA |= (1 << ADSC); // start ADC measurement
 206                 while (ADCSRA & (1 << ADSC) ); // wait till conversion complete
 207                 {
 208                         // We are detecting "video" if we have a value
 209                         // greater than some minimal value on ADC1/PB2.
 210                         // This approach requires a weak pulldown on the relevant
 211                         // video input to the circuit, but it beats not detecting anything.
 212                         // 255/50*4=20, thus 0.4V
 213                         if (ADCH > 20)
 214                         {
 215                                 // Make sure any signal generated by us does not leak back
 216                                 PORTB &= 0xEF; // Switch OFF VOut-switch for ATtiny
 217                                 // The next statement stops sync-generation, thus also image-generation..
 218                                 TIMSK &= ~(1<<OCIE0A); // Enable compare-mach-a interrupt
 219                                 // Reset Timer1 so we don't generate a TOVF..
 220                                 TCNT1 = 0;
 221                         }
 222                         // If we did not see a signal above the treshold, TCNT1 will continue
 223                         // to count up, until a TOV1 interrupt is generated.
 224                 }
 225         };
 226 }