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Changed hardware configuration. ATmega not supplies CLKO-clock to ATtiny, freeing...
[avrfbosd] / render.c
1 #include "render.h"
2 #include <avr/io.h>
3
4
5 extern volatile int buffer_position;
6 extern volatile uint8_t hres_bytes;
7 extern volatile char* screen_buffer;
8
9
10 void asm_render_line( void ) {
11 __asm__ __volatile__ (
12 ".macro outbit p" "\n\t"
13 "BST __tmp_reg__,7" "\n\t" // Store bit 7 to T
14 "BLD r16,7" "\n\t" // Load bit T into r16 bit number 7
15 "OUT \\p,r16" "\n\t" // Send contents of r16 to %[port]
16 "NOP" "\n\t" // Delay ...
17 "NOP" "\n\t" // Delay ...
18 "NOP" "\n\t" // Delay ...
19 ".endm" "\n\t"
20
21 "ADD r26,r28" "\n\t" // Add register Y to register X, low part
22 "ADC r27,r29" "\n\t" // Add high Y to X with carry from low part
23
24 "IN r16,%[port]" "\n\t" // Save port content to register 16
25 "RJMP start_line" "\n\t"
26
27 "loop_byte:" "\n\t" // Notice that in the macro we always use bit 7 and left-shift
28 "BST __tmp_reg__,6" "\n\t" // Here we use bit 6 without left-shift to output bit 0
29 "BLD r16,7" "\n\t" // of each byte (except the last bit on the line)
30 "OUT %[port],r16" "\n\t" // We do not have time for a left-shift, teh "extra cycle" was used for "dec-branch"
31 "NOP" "\n\t" // Delay ...
32 "NOP" "\n\t" // Delay ...
33
34 "start_line:" "\n\t"
35 "LD __tmp_reg__,X+" "\n\t" // Load from address pointed to by X into temporary register, then increment X-pointer
36
37 "outbit %[port]" "\n\t" // Output bit 7 using Macro
38 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
39 "outbit %[port]" "\n\t" // Output bit 6 using Macro
40 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
41 "outbit %[port]" "\n\t" // Output bit 5 using Macro
42 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
43 "outbit %[port]" "\n\t" // Output bit 4 using Macro
44 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
45 "outbit %[port]" "\n\t" // Output bit 3 using Macro
46 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
47 "outbit %[port]" "\n\t" // Output bit 2 using Macro
48 "LSL __tmp_reg__" "\n\t" // Left-shift for next bit
49 "outbit %[port]" "\n\t" // Output bit 1 using Macro
50
51 "DEC %[hr]" "\n\t" // Decrement num-bytes-remaining-in-resolution
52 "BRNE loop_byte" "\n\t" // Branch to loop6 if %[hres] != zero
53
54 "LSL __tmp_reg__" "\n\t" // Left-shift for last bit on the line
55 "outbit %[port]" "\n\t" // Output bit 0 using Macro.
56
57 "CBI %[port],7" "\n\t" // Clear our "display bit" to ensure we end on black
58
59 :
60 : [port] "i" (_SFR_IO_ADDR(PORTD)),
61 "x" (screen_buffer),
62 "y" (buffer_position),
63 [hr] "d" (hres_bytes)
64 : "r16"
65 );
66 }